1. Field of Invention
The present invention relates to a fabrication method of a flash memory. More particularly, the present invention relates to a method of fabricating an NAND flash memory structure which provides a higher density memory device array.
2. Description of Related Art
A conventional flash memory structure is characterized by a gate structure having two layers. One layer is a floating gate, fabricated from polysilicon for storing charges, and is usually in a floating status without being connected to any other circuits. Another layer is a control gate for controlling the date access to the floating gate. For example, in a NAND flash memory, each floating gate of the flash memory is connected to a word line (W/L) and each source/drain region of the flash memory is connected in series to a bit line (B/L). Flash memory is a very popular Erasable Programmable Read-Only Memory (EPROM) which can provide faster programming and erasing. Conventionally, the read/write function of the flash memory is performed using Fowler-Nordheim tunneling between the floating gate and the doped region, the rate of which depends on the electron transmission speed between the floating gate and the doped region.
Manufacturing flash memory at a minimized size is necessary in semiconductor process; i.e. the distribution of flash memory needs to have a higher density in order to conform to the process requirements. But, in this case, the extent to minimize the size of the flash memory is limited, if the flash memory conforms to the design rule. Moreover, it is very difficult to fabricate a tunneling oxide layer between the floating gate and the substrate when the thickness of the tunneling oxide layer is required to be very thin. It is especially difficult to perform the alignment step. It is important to precisely conform to the Shallow Trench Isolation (STI) process, so that the unnecessary shorts and leakage resulting between the device and the substrate are prevented.